In recent years, the high integration of LSI (Large Scaled Integrated Circuit) devices has come to be possible along with the progress of semiconductor manufacturing techniques. This has also made it possible to integrate both large capacity memories and large scaled logic circuits together on one semiconductor chip. With such a semiconductor chip, it is easy to increase the number of data I/O lines to thereby improve the data throughput between memory and logic circuit. This also makes it possible to reduce the power consumption of data I/O operations more and transfer data faster than in a case in which I/O pins provided outside the semiconductor chip are driven. The advantages of such a semiconductor chip are thus expected to be used more and more in the future.
There is a semiconductor chip in which a large capacity memory, a large scaled logic circuit, and a fast operation cache memory are combined. This semiconductor chip is intended to use a cache memory for reducing the difference of the operation speed between the large capacity memory and the large scaled logic circuit. Such a semiconductor chip is described, for example, in "an article by Toru Shimizu, et al., entitled "A Multimedia 32 b RISC Microprocessor with 16 Mb DRAM", 1966 IEEE International Solid-State Circuits Conference, Digest of Technical Papers pp. 216-217 (hereafter, to be referred to as the prior art technique 1)". According to this prior art technique 1, a 32-bit microprocessor, a 2 MB DRAM, and a 2 KB cache memory are connected to each other through a 128-bit wide internal bus. When 128-bit data is transferred, the operation is terminated in five cycles between the microprocessor and the DRAM and in one cycle between the microprocessor and the cache memory. Consequently, while the cache memory is hit, the number of data transfer cycles can be reduced to 1/5.